This invention relates to a semiconductor integrated circuit device, and more particularly relates to a high-speed semiconductor memory having parity bits, or to a semiconductor device including such a memory.
With the progress of large capacity memories, a memory structure, in which a memory cell array is divided into a plurality of blocks and a block is further divided into a plurality of mats, has been employed to reduce the number of circuits operated simultaneously, with a view toward reduction of power consumption.
For example, when data consisting of a plurality of bits is inputted or outputted to a single address, a certain single memory block is selected from a plurality of memory blocks and a certain plurality of memory cells is selected in a single memory mat in the memory block, and the data of a plurality of bits are outputted or inputted simultaneously.
In a high-speed semiconductor memory, all memory blocks are selected, and in each memory block, a memory cell in each single memory mat is selected, thus the data of a plurality of bits are outputted or inputted simultaneously.
In both cases, in a single semiconductor memory chip, the memory is divided into memory blocks of the n-th power of 2 (n is an integer).
In such a semiconductor memory, which is divided into memory blocks of the n-th power of 2, when the semiconductor memory has parity bits and it is required to change the number of input/output bits to different bit structures, the semiconductor memory is disadvantageous for reasons described hereinunder.
For example, it is assumed that a chip can have either a x36 bit structure or a x18 bit structure. In this case, if the smaller bit structure (x18) is realized, the input/output data bits are not distributed evenly to the plurality of memory blocks, so that a signal propagation path is required between the plurality of memory blocks. The signal propagation path hinders high speed processing, which is a disadvantage of this method.
For example, in a semiconductor memory having four memory blocks (the square of 2), the input/output bits of each block consist of nine bits when selecting the x36 bit structure. On the other hand, the distribution generates two types of input/output bits for the blocks, namely four bit memory blocks and five bit memory blocks when selecting the x18 bit structure.
Each block is structured so as to generate nine bits; therefore, when switching from x36 bits to x18 bits, a logic arrangement for outputting a one bit signal for each two adjacent bits (or inputting the signal to either bit) is necessary. Also, a logic arrangement is required so that the ninth bit is paired with one bit of another memory block and a signal of either bit is outputted (or the signal is inputted to either bit).
Therefore, bit signals other than the residual ninth bit are transferred using a path in the corresponding memory blocks; however, the signal line of the residual ninth bit is required to be connected to the adjacent memory block, and the connection results in a problem of increased propagation delay time on a signal bass line.